Strained Silicon Layer in CMOS Technology

Abstract

Semiconductor industry is currently facing with the
fact that conventional submicron CMOS technology is
approaching the end of their capabilities, at least when it comes to
scaling the dimensions of the components. Therefore, much
attention is paid to device technology that use new technological
structures and new channel materials. Modern technological
processes, which mainly include ultra high vacuum chemical
vapor deposition, molecular beam epitaxy and metal-organic
molecular vapor deposition, enable the obtaining of ultrathin,
crystallographically almost perfect, strained layers of high purity.
In this review paper we analyze the role that such layers have in
modern CMOS technologies. It’s given an overview of the
characteristics of both strain techniques, global and local, with
special emphasis on performance of NMOS biaxial strain and
PMOS uniaxial strain. Due to the improved transport properties
of strained layers, especially high mobility of charge carriers, the
emphasis is on mechanisms to increase the charge mobility of
strained silicon and germanium, in light of recent developments in
CMOS technology.