Cost Effective Implementation of Fixed Point Adders for LUT based FPGAs using Technology Dependent Optimizations

Abstract

Modern day field programmable gate arrays
(FPGAs) have very huge and versatile logic resources resulting in
the migration of their application domain from prototype
designing to low and medium volume production designing.
Unfortunately most of the work pertaining to FPGA
implementations does not focus on the technology dependent
optimizations that can implement a desired functionality with
reduced cost. In this paper we consider the mapping of simple
ripple carry fixed-point adders (RCA) on look-up table (LUT)
based FPGAs. The objective is to transform the given RCA
Boolean network into an optimized circuit netlist that can
implement the desired functionality with minimum cost. We
particularly focus on 6-input LUTs that are inherent in all the
modern day FPGAs. Technology dependent optimizations are
carried out to utilize this FPGA primitive efficiently and the
result is compared against various adder designs. The
implementation targets the XC5VLX30-3FF324 device from
Xilinx Virtex-5 FPGA family. The cost of the circuit is expressed
in terms of the resources utilized, critical path delay and the
amount of on-chip power dissipated. Our implementation results
show a reduction in resources usage by at least 50%; increase in
speed by at least 10% and reduction in dynamic power
dissipation by at least 30%. All this is achieved without any
technology independent (architectural) modification.