Single-Stage Operational Transconductance Amplifier Design in UTBSOI Technology Based on gm/Id Methodology

Abstract

The downscaling of complementary metal-oxidesemiconductor
(CMOS) technology is approaching its limits
imposed by short-channel effects (SCE), thereby multi-gate
MOSFETs have been proposed to extend the scalability. Ultrathin-
body silicon-on-insulator (UTBSOI) transistor is one of the
dual-gated devices which offers better immunity towards SCEs.
In this paper, two designs have been proposed for single-stage
operational transconductance amplifiers (OTA) using the CMOS
and UTBSOI. The CMOS based OTA (CMOS-OTA) has been
designed where sizing (W/L) of the constituting MOSFETs have
been evaluated through gm/Id methodology and the same OTA
topology has been simulated using UTBSOI (UTBSOI-OTA)
considering the same W/L. The DC simulation is carried out over
the BSIM3v3 model to store the operating point parameters in
the form of graphical models. The mathematical expressions for
performance specifications have been applied over the graphical
models to evaluate the required W/L. Individual comparisons
between the two proposed designs have also been carried out for
further applications. Based on simulation results at the schematic
level, the UTBSOI-OTA has higher DC gain of 33.26% and
lesser power consumption of 2.81% over the CMOS-OTA.
Moreover, comparative analysis of performance parameters like
DC gain and common-mode rejection ratio (CMRR), have been
compared with the best-reported paper so far. In addition to
this, the UTBSOI-OTA has been applied to practical integrator
circuits for further verification.