On the Implementation of Multi-bit Inexact Adder Cells and Application towards Image De-noising

Abstract

Inexact computing is an attractive concept for
digital signal processing at the submicron regime. This paper
proposes 2-bit inexact adder cell and further escalate to 4-bit, and
8-bit inexact adder and error metrics have been evaluated
mathematically for such adder cells. The approximated design has
been proposed through the simplification of the K-Maps, which
leads to a substantial reduction in the propagation delay as well as
energy consumption. The proposed design has been verified
through the Cadence Spectre and performance parameters (such
as delay, power consumption) have been evaluated through CMOS
gpdk45 nm technology. Furthermore, the proposed design has
been applied to image de-noising application where the
performance of the images like Peak Signal to Noise Ratio (PSNR),
Normalized Correlation Coefficient (NCC) and Structural
Similarity Index (SSIM) has been analyzed through MATLAB,
which offer the substantial improvement from its counterpart.