Pattern-Based Approach to Current Density Verification

Authors

  • Vazgen Melikyan
  • Eduard Babayan
  • Ashot Harutyunyan

DOI:

https://doi.org/10.7251/ELS1216077M

Abstract

Methodology of static verification of current density based on layout patterns common in IC designs is proposed. The methodology is based on pre-calculation of current density distribution for common layout patterns. Then using the obtained data to calculate current densities of large circuits by partitioning them to selected patterns. Presented experimental results show the effectiveness of the approach.

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Published

2012-06-15

Issue

Vol. 16 No. 1 (2012)

Section

Articles

License

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