The Decomposition of DSP’s Control Logic Block for Power Reduction

Authors

  • Borisav Jovanovic
  • Milunka Damnjanović

DOI:

https://doi.org/10.7251/ELS1216085J

Abstract

The paper considers the architecture and low power design aspects of the digital signal processing block embedded into a three-phase integrated power meter IC. Utilized power reduction techniques were focused on the optimization of control logic block. The operations that control unit performs are described together with power optimization results.

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Published

2012-06-15

Issue

Vol. 16 No. 1 (2012)

Section

Articles

License

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