ELECTRONICS

Editor’s Column

2021-07-08T10:30:12+02:00

THE second issue of Electronics journal in December 2020
brings new research in the fields of image processing and
integrated circuit design but also many challenges caused by
the COVID-19 pandemic that affected all the aspects of our
lives globally. Unfortunately, COVID-19 also brought away
our friend and renowned member of the Editorial Board of the
journal “Electronics”, prof. Ninoslav Stojadinovi´c who passed
away on 25 December 2020. In honor to this great scientist,
educator, and influential leader, our founder and honorary
Editor-in-Chief, prof. Branko Doki´c, accepted to pass to our
knowledge at least a tiny part of prof. Stojadinovi´c’s rich and
fruitful professional life within “In Memoriam” section.

In Memoriam – Prof. Ninoslav Stojadinovi´c

2021-07-08T10:34:02+02:00

ON December 25, 2020, our friend, renowned scientist,
educator, world renowned expert, and member of the
Editorial Board of journal “Electronics”,
Ninoslav Stojadinovi´c
(20.09.1950–25.12.2020) lost the battle for his life against
Covid-19.

A Novel Unsupervised Approach for Land Classification Based on Touzi Scattering Vector Model in the Context of Very High Resolution PolSAR Imagery

2021-07-08T10:38:13+02:00

With the popularization of very high resolution polarimetric
synthetic aperture radar image dataset, it is essential
to re-investigate the classification scheme for 2-D land cases. The
Touzi scattering vector model, a unique and roll-invariant decomposition
solution, is employed to extract the scattering properties
of different land covers. The parameters of Touzi decomposition
act as input dataset for initial classification. A novel classifying
algorithm is put forward by means of integrating the Touzi decomposition
with conventional Wishart statistical models. Quantitative
experiments are then conducted using uninhabited aerial
vehicle synthetic aperture radar sample data for evaluating the
performance of this new proposed approach. It can be concluded
from the experimental results that the new proposed method is superior
to the classical method in terms of producer accuracy, user
accuracy, and overall accuracy.

A Full Adder Design with CNFETs for Real Time, Fault Tolerant and Mission Critical Applications

2021-07-08T10:41:13+02:00

The VLSI based circuits often pose challenges in the
form of various faults (such as transient faults, permanent faults,
stuck-at-faults). These faults appear even after testing also. They
occur because of reduction in the size of the circuit or during real-
time implementation, as these faults are difficult to detect. It is
very important to detect and rectify all such faults to make the system
foolproof and achieve expected functionality. In this paper, 12
transistors based, full adder circuit (12T-FAC) using Carbon Nanotube
Field Effect Transistor (CNFET) technology is proposed. The
proposed design based on CNFET provides high fault resistance
towards transient, permanent faults and works with least power,
delay and power-delay product (PDP). Later, features like fault
detection and correction circuit have been added in 12T-FAC. The
final version of full adder circuit capable of correcting errors has
been used in designing applications like multipliers. The proposed
full adder circuit was designed with CNFET technology, simulated
at 32 nm with supply voltage +0.9 V using the Cadence Virtuoso
CAD tool. The model used is Stanford PTM.

Sensitivity Analysis of the UTBSOI Transistor based Two-Stage Operational Amplifier

2021-07-08T10:43:53+02:00

In the nanoscale domain, the MOSFETs are prone to
various physical effects due to their shorter channel region known
as short-channel effects (SCE). The researchers have proposed
an advanced structure of MOSFET known as the ultrathinbody
silicon-on-insulator (UTBSOI) to overcome the limitations
of SCEs. The UTBSOI is a type of double-gate (DG) MOSFET
having superior controllability of gates over the shorter channel
region. Nowadays, the UTBSOI MOSFETs can be adopted in
the circuit simulators through the use of a device model named
BSIM-IMG. The BSIM-IMG has made it possible for the circuit
designers to simulate any UTBSOI based analog blocks like
operational amplifiers (opamp). The performance parameters
of an opamp are very much sensitive to any perturbation in
size (W/L) of the constituent MOSFETs, that may cause a
drastic change in the output. In this paper, the sensitivity analysis
procedure has been proposed for the CMOS and UTBSOI based
two-stage opamps as the function of perturbation in W/L. In
addition to this, an algorithm has also been presented to do
the same. From the simulation results, it is observed that the
sensitivity of the UTBSOI based opamp (UTBSOI-opamp) is
larger than that of CMOS based opamp (CMOS-opamp).